DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 537

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
(n)
Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing
occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change
in duty cycle at synchronous counter clearing.
Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval
at the trough as indicated by (10) or (11) in figure 12.56. When synchronous clearing occurs
outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb
interval at the trough, if synchronous clearing occurs in the initial value output period (indicated
by (1) in figure 12.56) immediately after the counters start operation, initial value output is not
suppressed.
When using the initial output suppression function, make sure to set compare registers TGRB_3,
TGRA_4, and TGRB_4 to a value twice or more the setting of dead time data register TDDR. If
synchronous clearing occurs with the compare registers set to a value less than twice the setting of
TDDR, the PWM output dead time may be too short (or nonexistent) or illegal active-level PWM
negative-phase output may occur during the initial output suppression interval. For details, see
section 12.7.23, Notes on Output Waveform Control During Synchronous Counter Clearing in
Complementary PWM Mode.
In the MTU2, synchronous clearing generated in channels 0 to 2 in the MTU2 can cause counter
clearing.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Output Waveform Control at Synchronous Counter Clearing in Complementary PWM
Mode
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
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