DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 181

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
IRQ
RESBANK instruction
Instruction (instruction replacing
interrupt exception handling)
First instruction in
interrupt service routine
[Legend]
m1:
m2:
m3:
m4:
Figure 6.9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in
interrupt service routine
[Legend]
m1:
m2:
m3:
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Restoration of banked registers
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Figure 6.8 Example of Pipeline Operation when IRQ Interrupt is Accepted
Instruction Execution (Register Banking with Register Bank Overflow)
2 Icyc + 3 Bcyc + 1 Pcyc
(Register Banking with Register Bank Overflow)
2 Icyc + 3 Bcyc + 1 Pcyc
F
D
Interrupt acceptance
E
2 Icyc + 17(m4)
F
M
M
D
3 Icyc
3 Icyc + m1 + m2
M
E
Interrupt acceptance
...
E
M
m1
1 Icyc + m1 + m2 + 2(m4)
M
m4 m4
M
D
Section 6 Interrupt Controller (INTC)
m2
M
E
M
W
E
m3
M
F
m1 m2 m3
M
...
...
M
Page 153 of 1190
M
M
...
F
...
...
D
D