DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 344

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Direct Memory Access Controller (DMAC)
Page 316 of 1190
Bit
2
Bit Name
DACT
Initial
Value
Undefined R/W
R/W
Description
DMA Active Signal Output for Destination
This bit is used to control the output of the DMA-active
signal (DACT) for the destination corresponding to the
request source setting in the DCTG bits.
When this bit is set to "0", output of the DACT signal is
disabled and fixed high unless the level changes
because of the SACT bit setting.
When this bit is set to "1", output of the DACT signal is
valid ("L") from the next cycle after the start of the
DMAC read cycle.
However, while output of the DACT signal is enabled
when the DMA request source selection (DCTG) bits
are set for software triggering, a valid DACT signal
cannot be output when the requesting source is an on-
chip peripheral circuit (DCTG), regardless of the
setting of the DACT bit.
0: Stops output of the DMA-active signal for the
1: Selects output of the DMA-active signal for the
destination
destination during write access
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010