DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 393

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
(b)
Maximum transfer speed from an on-chip CPU block as the source (0 wait) to an external device
(2 write cycles).
• Cycle-stealing transfer mode
• Pipelined transfer mode
Maximum transfer speed from an external device (4 read cycles) to an on-chip CPU block source
(0 wait)
• Cycle-stealing transfer mode
• Pipelined transfer mode
Maximum transfer speed from an external device (4 read cycles) to an external device (2 write
cycles)
• Cycle-stealing transfer mode
• Pipelined transfer mode
Note: Access to external devices is controlled by the settings of the BSC control registers. For
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
No pipelined transfer is possible between the external devices.
Transfer to External Devices
details, see section 9, Bus State Controller (BSC).
4 bytes / (1 read cycle + 2 write cycles + 1 idle cycle) × 60 MHz = 60 Mbytes/sec
4 bytes / (2 write cycles)× 60 MHz = 120 Mbytes/sec
4 bytes / (4 read cycles + 1 write cycle + 1 idle cycle) × 60 MHz = 39.6 Mbytes/sec
4 bytes / (4 read cycles)× 60 MHz = 60 Mbytes/sec
4 bytes / (4 read cycles + 2 write cycles + 1 idle cycle) × 60 MHz = 34.2 Mbytes/sec
Section 11 Direct Memory Access Controller (DMAC)
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