DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 698

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
• Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
• The quantity of data in the transmit and receive FIFO registers and the number of receive
• A time-out error (DR) can be detected when receiving in asynchronous mode.
Figure 16.1 shows a block diagram of the SCIF.
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TxD
SCK
RxD
receive-error interrupts are requested independently.
power.
errors of the receive data in the receive FIFO register can be ascertained.
[Legend]
SCRSR:
SCFRDR:
SCTSR:
SCFTDR:
SCSMR:
SCSCR:
SCFRDR (16 stage)
SCRSR
Receive shift register
Receive FIFO data register
Transmit shift register
Transmit FIFO data register
Serial mode register
Serial control register
Parity check
SCFTDR (16 stage)
Figure 16.1 Block Diagram of SCIF
Parity generation
SCTSR
Module data bus
SCFSR:
SCBRR:
SCSPTR:
SCFCR:
SCFDR:
SCLSR:
Transmission/reception
control
Serial status register
Bit rate register
Serial port register
FIFO control register
FIFO data count register
Line status register
SCSPTR
SCSMR
SCFDR
SCFCR
SCFSR
SCSCR
SCLSR
External clock
Clock
Baud rate
generator
SCIF
SCBRR
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
P
P /4
P /16
P /64
TXI
RXI
ERI
BRI
Peripheral
bus