DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 43

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Classification
Direct memory
access controller
(DMAC)
Multi-function
timer pulse unit 2
(MTU2)
Symbol
DREQ3 to
DREQ0
DACK3 to
DACK0
DACT3 to
DACT0
DTEND3 to
DTEND0
TCLKA,
TCLKB,
TCLKC,
TCLKD
TIOC0A,
TIOC0B,
TIOC0C,
TIOC0D
TIOC1A,
TIOC1B
TIOC2A,
TIOC2B
TIOC3A,
TIOC3B,
TIOC3C,
TIOC3D
TIOC4A,
TIOC4B,
TIOC4C,
TIOC4D
TIOC5U,
TIOC5V,
TIOC5W
I/O
I
O
O
O
I
I/O
I/O
I/O
I/O
I/O
I
Name
DMA-transfer
request
DMA-transfer
request
acknowledge
DMA-transfer
request active
DMA-transfer end
output
MTU2 timer clock
input
MTU2 input
capture/output
compare
(channel 0)
MTU2 input
capture/output
compare
(channel 1)
MTU2 input
capture/output
compare
(channel 2)
MTU2 input
capture/output
compare
(channel 3)
MTU2 input
capture/output
compare
(channel 4)
MTU2 input
capture
(channel 5)
Function
Input pins to receive external
requests for DMA transfer
Output pins for signals indicating
acknowledge of external requests
from external devices
Output pins for signals indicating
DMA active in response to external
requests from external devices
Output pins for DMA transfer end
External clock input pins for the timer
The TGRA_0 to TGRD_0 input
capture input/output compare
output/PWM output pins.
The TGRA_1 and TGRB_1 input
capture input/output compare
output/PWM output pins.
The TGRA_2 and TGRB_2 input
capture input/output compare
output/PWM output pins.
The TGRA_3 to TGRD_3 input
capture input/output compare
output/PWM output pins.
The TGRA_4 and TGRB_4 input
capture input/output compare
output/PWM output pins.
The TGRU_5, TGRV_5, and
TGRW_5 input capture input/dead
time compensation input pins.
Section 1 Overview
Page 15 of 1190