DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 887

IC SH7201 MPU ROMLESS 176LQFP

DS72011RB120FPV

Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet

Specifications of DS72011RB120FPV

Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Notes: 1. SW reset could be performed at any time by setting MCR[0] = 1.
Configuration Mode
2. Mailboxes are comprised of RAMs, therefore, please initialize all the mailboxes enabled by MBC.
3. It takes approximately one bit time for GSR[3] to be cleared to 0.
4. If there is no TXPR set, RCAN-ET will receive the next incoming message.
If there is a TXPR(s) set, RCAN-ET will start transmission of the message and will be arbitrated by the CAN bus.
If it loses the arbitration, it will become a receiver.
IRR[0] = 1, GSR[3] = 1 (automatically)
(automatically in hardware reset only)
RTR, IDE, MBC, MBIMR, DART,
(STD-ID, EXT-ID, LAFM, DLC,
ATX, NMC, Message-Data)*
Clear Required IMR Bits
Power On/SW Reset*
Set Bit Timing (BCR)
Configure MCR[15]
Mailbox Setting
clear IRR[0] Bit
Clear MCR[0]
MCR[0] = 1
Figure 19.6 Reset Sequence
1
2
Receive*
Section 19 Controller Area Network (RCAN-ET)
Detect 11 recessive bits and
RCAN-ET is in Tx_Rx Mode
Set TXPR to start transmission
or stay idle to receive
Join the CAN bus activity
4
GSR[3] = 0?
Yes
Transmission_Reception
(Tx_Rx) Mode
Transmit*
Page 859 of 1190
No*
4
3

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