r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 999

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

23.3.87 Overflow Alert FIFO Threshold Register (FCFTR)

FCFTR is a 32-bit readable/writable register that sets the flow control of the E-MAC. The

threshold can be set by the size of the receive FIFO data (bits RFD[7:0]) and the number of

receive frames (bits RFF[4:0]).

If the same receive FIFO size as set by the FIFO depth register (FDR) is set when flow control is

turned on according to the RFD setting condition, flow control is turned on with (FIFO data size •

64) bytes. For instance, when the RFD bits in FDR = 7 and the RFD bits in this register = 7, flow

control is turned on when (2,048 • 64) bytes of data is stored in the receive FIFO. The value set in

the RFD bits in this register should be equal to or less than that set in the RFD bits in FDR.

Flow control is turned on when either of the setting conditions of bits RFF[4:0] and bits RFD[7:0]

is satisfied. Flow control is turned off when neither of the conditions is satisfied (release).

Initial value:

These bits are always read as 0. The write value should

always be 0.

Receive FIFO Overflow Alert Signal Output Threshold

H'00: When one receive frame has been stored in the

H'01: When two receive frames have been stored in the

H'16: When 23 receive frames have been stored in the

H'17: When 24 receive frames have been stored in the

receive FIFO

Section 23 Gigabit Ethernet Controller (GETHER)

Rev. 1.00 Oct. 01, 2007 Page 933 of 1956

REJ09B0256-0100