r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 675

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

5. Hereafter, steps 2 and 4 are repeated until the DME or DE bit is cleared to 0, or an NMI
As explained above, a repeat mode transfer enables sequential voice compression by changing
buffer for storing data received consequentially and a data buffer for processing signals
alternately.
14.4.6
In a reload mode transfer, according to the settings of bits RPT[2:0] in CHCR, the value set in
SARB/DARB is set to SAR/DAR and the value of bits TCRB[23:16] is set in bits TCRB[7:0] at
each transfer set in the bits TCRB[7:0], and the transfer is repeated until TCR becomes 0 without
specifying the transfer settings again. A reload mode transfer is effective when repeating data
transfer with specific area. Figure 14.12 shows the operation of reload mode transfer.
When a reload mode transfer is executed, TCRB is used as a reload counter. Set TCRB according
to section 14.3.6, DMA Transfer Count Registers (TCRB0 to TCRB3).
interrupt is generated. Note that if the HE bit is not cleared in the procedure 3 or if the TE bit is
not cleared in the procedure 4, then the transfer is stopped according to the condition of both
the HE and the TE bits are set to 1.
Transfer request
Reload Mode Transfer
DMAC
Reload controller
Figure 14.12 Reload Mode Transfer
Section 14 Direct Memory Access Controller (DMAC)
Reload signal
Bits RPT[2:0]
Rev. 1.00 Oct. 01, 2007 Page 609 of 1956
Transfer counter
Reload counter
SARB/DARB
SAR/DAR
CHCR
TCRB
TCR
REJ09B0256-0100