r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 69
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r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
- Current page: 69 of 2026
- Download datasheet (12Mb)
Item
FPU
Features
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Note:
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On-chip floating-point coprocessor
Supports single-precision (32 bits) and double-precision (64 bits)
Supports IEEE754-compliant data types and exceptions
Two rounding modes: Round to Nearest and Round to Zero
Handling of denormalized numbers: Truncation to zero or interrupt
generation for IEEE754 compliance
Floating-point registers: 32 bits × 16 words × 2 banks
(single-precision × 16 words or double-precision × 8 words) × 2 banks
32-bit CPU-FPU floating-point communication register (FPUL)
Supports FMAC (multiply-and-accumulate) instruction
Supports FDIV (divide) and FSQRT (square root) instructions
Supports FLDI0/FLDI1 (load constant 0/1) instructions
Instruction execution times
Latency (FADD/FSUB): 3 cycles (single-precision), 5 cycles (double-
Latency (FMAC/ FMUL): 5 cycles (single-precision), 7 cycles (double-
Pitch (FADD/FSUB): 1 cycle (single-precision/double-precision)
Pitch (FMAC/FMUL): 1 cycle (single-precision), 3 cycles (double-
3-D graphics instructions (single-precision only):
4-dimensional vector conversion and matrix operations (FTRV): 4
4-dimensional vector (FIPR) inner product: 1 cycle (pitch), 5 cycles
Ten-stage pipeline
precision)
precision)
precision)
cycles (pitch), 8 cycles (latency)
(latency)
FMAC is supported for single-precision only.
Rev. 1.00 Oct. 01, 2007 Page 3 of 1956
Section 1 Overview
REJ09B0256-0100
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