r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1170

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 27 Serial Communication Interface with FIFO (SCIF)
5. When modem control is enabled, the SCIF_RTS signal is output when SCFRDR is empty.
Figure 27.14 shows an example of the operation when modem control is used.
27.4.3
Clocked synchronous mode, in which data is transmitted or received in synchronization with clock
pulses, is suitable for fast serial communication.
Since the transmitter and receiver are independent units in the SCIF, full-duplex communication
can be achieved by sharing the clock. Both the transmitter and receiver have a 64-stage FIFO
buffer structure, so that data can be read or written during transmission or reception, enabling
continuous data transfer and reception.
Figure 27.15 shows the general format for clocked synchronous communication.
Rev. 1.00 Oct. 01, 2007 Page 1104 of 1956
REJ09B0256-0100
When SCIF0_RTS is 0, reception is possible. When SCIF_RTS is 1, this indicates that
SCFRDR contains bytes of data equal to or more than the SCIF_RTS output active trigger
number. The SCIF_RTS output active trigger value is specified by bits 10 to 8 in the FIFO
control register (SCFCR). For details, see section 27.3.9, FIFO control register (SCFCR). In
addition, SCIF_RTS is also 1 when the RE bit in SCSCR is cleared to 0.
SCIF_RXD
SCIF_RTS
Serial data
Synchronization
clock
Serial data
Note: * High except in continuous transfer
Operation in Clocked Synchronous Mode
Figure 27.14 Sample Operation Using Modem Control (SCIF0_RTS)
Figure 27.15 Data Format in Clocked Synchronous Communication
Start
bit
0
Don't care
D0
*
D1 D2
LSB
Bit 0
Bit 1
(Only in Channel 0)
One unit of transfer data (character or frame)
D7 0/1 1
Parity
bit
Bit 2
Stop
bit
Bit 3
Bit 4
Bit 5
Start
bit
0
Bit 6
Bit 7
MSB
Don't care
*