r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 465

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

The byte control SRAM interface is a memory interface that outputs a byte-select strobe (WEn) in

both read and write bus cycles. This interface has 16-bit data pins and can be connected to SRAM

having an upper byte select strobe and lower select strobe functions, such as UB and LB.

Areas 1 and 4 can be specified as a byte control SRAM interface. However, when these areas are

set to the MPX interface, the MPX interface has priority.

The write timing for the byte control SRAM interface is identical to that of a normal SRAM

In read operations, on the other hand, the WEn pin timing is different. In a read access, only the

WE signal for the byte being read is asserted. Assertion is synchronized with the falling edge of

the CLKOUT clock in the same way as for the WE signal, while negation is synchronized with the

rising edge of the CLKOUT clock in the same way as for the RD signal.

In 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width.

The first access is performed on the data for which there was an access request, and the remaining

accesses are performed in wrap around method according to the set bus width. The bus is not

released during this transfer.

Figure 11.37 shows an example of a byte control SRAM connection, and figures 11.38 to 11.40

show examples of byte-control SRAM read cycles.

Byte Control SRAM Interface

Figure 11.34 Example of 32-Bit Data-Width Byte-Control SRAM

Section 11 Local Bus State Controller (LBSC)

Rev. 1.00 Oct. 01, 2007 Page 399 of 1956

I/O15 to I/O0

I/O15 to I/O0

64K × 16-bit

REJ09B0256-0100