r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 483

no-image

r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
12.4.1
Initial value:
Initial value:
Initial value:
Initial value:
Bit
63 to 49 
48
47, 46
Note: * Depends on the setting of external pins (MD5).
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Memory Interface Mode Register (MIM)
Bit Name
BOMODE0
BOMODE1,
R/W
63
47
BOMODE
31
15
R
R
R
0
0
0
R/W
62
46
30
14
R
R
R
0
0
0
LOCK
Initial
Value
All 0
0
All 0
61
45
29
13
R
R
R
R
0
0
0
R/W
R/W
PC
KE
60
44
28
12
R
R
0
0
0
R/W
R
R
R/W
R/W
59
43
27
11
R
R
R
0
0
1
0
R/W
58
42
26
10
R
R
R
0
0
1
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
This bit is always read as 0. The write value should
always be 0.
Access Mode Switch
Switch access modes for the DDR-SDRAM.
The DDRIF supports two DDR-SDRAM access modes.
For details on the operation in each mode, see section
12.5.4, DDR-SDRAM Access Mode.
00: Bank open mode
01: Bank close mode
Other than above: Setting prohibited
DRE
R/W
R/W
57
41
25
R
R
0
0
0
9
0
R/W
END
IAN
56
40
24
R
R
R
0
0
0
8
R/W
55
39
23
R
R
R
0
0
0
7
0
Section 12 DDR-SDRAM Interface (DDRIF)
DRI[12:0]
Rev. 1.00 Oct. 01, 2007 Page 417 of 1956
R/W
54
38
22
R
R
R
0
0
0
6
0
R/W
53
37
21
R
R
R
0
0
1
5
0
R/W
52
36
20
R
R
R
0
0
1
4
0
DLLEN
R/W
R/W
51
35
19
R
R
0
0
0
3
0
REJ09B0256-0100
R/W
SEL
50
34
FS
18
R
R
R
0
0
1
2
0
MODE
R/W
R/W
49
33
17
R
R
0
R
0
0
1
0
DCE
R/W
R/W
48
32
16
R
R
0
0
0
0
0

Related parts for r5s77631ay266bgv