r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 952

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 23 Gigabit Ethernet Controller (GETHER)
23.3.53 CAM Entry Table POST4 Register (TSU_POST4)
When using the CAM, the conditions for referring to each CAM entry table can be specified by
using the TSU_POST1 to TSU_POST4 registers. TSU_POST4 specifies the conditions for
referring to TSU_ADRH24 to TSU_ADRH31 and TSU_ADRL24 to TSU_ADRL31. The settings
of this register are valid when the POSTENL bit in TSU_FWSLC is set to 1.
Rev. 1.00 Oct. 01, 2007 Page 886 of 1956
REJ09B0256-0100
Bit
31 to 28
27 to 24
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
POST24[3:0]
POST25[3:0]
R/W
R/W
31
15
0
0
POST24[3:0]
POST28[3:0]
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
All 0
All 0
Initial
Value
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W Description
R/W These bits set the conditions for referring to CAM entry
R/W These bits set the conditions for referring to CAM entry
POST25[3:0]
R/W
POST29[3:0]
R/W
26
10
0
0
table 24. By setting multiple bits to 1, multiple
conditions can be selected.
POST24[3]: CAM entry table 24 is referred to in port 0
POST24[2]: CAM entry table 24 is referred to in port 0
POST24[1]: CAM entry table 24 is referred to in port 1
POST24[0]: CAM entry table 24 is referred to in port 1
table 25. By setting multiple bits to 1, multiple
conditions can be selected.
POST25[3]: CAM entry table 25 is referred to in port 0
POST25[2]: CAM entry table 25 is referred to in port 0
POST25[1]: CAM entry table 25 is referred to in port 1
POST25[0]: CAM entry table 25 is referred to in port 1
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
R/W
R/W
reception.
to 1 relay.
reception.
to 0 relay.
reception.
to 1 relay.
reception.
to 0 relay.
23
0
7
0
R/W
R/W
POST26[3:0]
POST30[3:0]
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
R/W
R/W
POST27[3:0]
POST31[3:0]
18
0
2
0
R/W
17
0
1
0
R/W
R/W
16
0
0
0

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