r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 46

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)
Figure 23.1 Configuration of GETHER ..................................................................................... 784
Figure 23.2 GETHER Data Path and Various Settings .............................................................. 938
Figure 23.3 Relationship between Transmit Descriptor and Transmit Buffer............................ 940
Figure 23.4 Relationship between Receive Descriptor and Receive Buffer ............................... 946
Figure 23.5 Relationship between Transmit Descriptor and Transmit Buffer............................ 952
Figure 23.6 Relationship between Receive Descriptor and Receive Buffer ............................... 953
Figure 23.7 Relationship between Transmit/Receive Descriptor and Descriptor Pointing
Registers.................................................................................................................. 955
Figure 23.8 Sample Transmission Flowchart (Single-Frame/Two-Description)........................ 958
Figure 23.9 E-MAC Transmitter State Transitions..................................................................... 960
Figure 23.10 E-MAC Receiver State Transitions ....................................................................... 963
Figure 23.11 Sample Reception Flowchart (Single-Frame/Two-Descriptor)............................. 965
Figure 23.12 E-DMAC Operation after Transmit Error ............................................................. 971
Figure 23.13 E-DMAC Operation after Receive Error............................................................... 972
Figure 23.14 Padding Insertion in Receive Data ........................................................................ 973
Figure 23.15 Outlines of Qtag Additional Functions.................................................................. 982
Figure 23.16 Comparison of Normal Ethernet Frame and IEEE802.1Q Frame (with Qtag)...... 983
Figure 23.17 MII Frame Transmit Timing (Normal Transmission) ........................................... 984
Figure 23.18 MII Frame Transmit Timing (Collision) ............................................................... 984
Figure 23.19 MII Frame Transmit Timing (Transmit Error) ...................................................... 985
Figure 23.20 MII Frame Receive Timing (Normal Reception) .................................................. 985
Figure 23.21 MII Frame Receive Timing (Reception Error (1)) ................................................ 985
Figure 23.22 MII Fame Receive Timing (Reception Error (2)).................................................. 985
Figure 23.23 GMII/MII Fame Receive Timing (Normal Reception) ......................................... 986
Figure 23.24 GMII/MII Fame Receive Timing (with Carrier Extension) .................................. 986
Figure 23.25 GMII/MII Fame Receive Timing (Burst Reception)............................................. 986
Figure 23.26 GMII/MII Fame Receive Timing (Reception Error) ............................................. 987
Figure 23.27 GMII/MII Fame Receive Timing (Error with Carrier Extension) ......................... 987
Figure 23.28 GMII/MII Fame Receive Timing (False Carrier Indication)................................. 987
Figure 23.29 RMII Fame Receive Timing (Normal 100-Mbps Reception) ............................... 988
Figure 23.30 RMII Fame Receive Timing
(100-Mbps Reception with Illegal Carrier Detected)............................................ 988
Figure 23.31 RMII Fame Transmit Timing (Normal 100-Mbps Transmission)......................... 988
Figure 23.32 MII Management Frame Format ........................................................................... 989
Figure 23.33 1-Bit Data Write Flowchart................................................................................... 990
Figure 23.34 Bus Release Flowchart (TA in Read in Figure 23.33)........................................... 990
Figure 23.35 1-Bit Data Read Flowchart.................................................................................... 991
Figure 23.36 Independent Bus Release Flowchart (IDLE in Write in Figure 23.33) ................. 991
Figure 23.37 MII-RMll Conversion Circuit ............................................................................... 992
Rev. 1.00 Oct. 01, 2007 Page xlvi of lxvi