r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 892
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r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
- Current page: 892 of 2026
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Section 23 Gigabit Ethernet Controller (GETHER)
23.3.14 CRC Error Frame Receive Counter Register (CEFCR)
CEFCR is a 16-bit counter that indicates the number of times a frame with a CRC error was
received. When the value in this register reaches H'0000FFFF, count-up is halted. This register is
cleared to 0 when it is read with the TRCCM bit in ECMR set to 1. When the TRCCM bit in
ECMR is 0, this register is cleared to 0 by writing H'11111111.
Rev. 1.00 Oct. 01, 2007 Page 826 of 1956
REJ09B0256-0100
Bit
31 to 16
15 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
CEFC[15:0] All 0
R/W
31
15
R
0
0
R/W
30
14
R
0
0
R/W
29
13
R
0
0
Initial
Value
All 0
R/W
28
12
R
0
0
R/W
27
11
R/W
R
R/W
R
0
0
R/W
26
10
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
CRC Error Frame Count
These bits indicate the number of CRC error frames
received.
R/W
25
R
0
9
0
R/W
CEFC[15:0]
24
R
0
8
0
R/W
23
R
0
7
0
R/W
22
R
0
6
0
R/W
21
R
0
5
0
R/W
20
R
0
4
0
R/W
19
R
0
3
0
R/W
18
R
0
2
0
17
R
0
1
0
R/W
16
R
0
0
0
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