r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 499

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

12.5.4
The DDRIF supports the following two DDR-SDRAM access modes. Each mode can be set using
the BOMODE bits in MIM.
Bank Open Mode: The DDR-SDRAM is accessed without the PRE command immediately after
memory read or memory write, meaning that the bank is always open. This mode is useful for
applications in which bank hits continue to occur during consecutive memory accesses. When a
bank miss occurs, the PRE command is automatically issued.
Bank Close Mode: Immediately after memory read or memory write, the PRE command is output
and the bank is closed. This mode is useful for applications in which a bank hit does not continue
to occur in consecutive memory accesses.
12.5.5
(1)
The self-refresh mode is a standby state where the refresh timing and refresh addresses are
generated in the DDR-SDRAM. The self-refresh state is retained even if the CPU enters the sleep
mode after the self-refresh mode is set by setting the DRE and RMODE bits in MIM to 1. If the
sleep mode of CPU is canceled due to an interrupt, the self-refresh state is retained.
Although the self-refresh state is entered through the register setting of the DDRIF, the following
sequence should be used.
[Transition to self-refresh state]
1. Confirm that the transaction to the memory controller is completed.
2. Through software control, set the SMS bits in SCR to issue the PREALL command. This
3. To make the DDR-SDRAM enter the self-refresh state, set the DRE and RMODE bits in MIM.
4. The memory controller automatically issues the self-refresh command and set the CKE pin
closes any DDR-SDRAM bank that was open. After that, use the SMS bits in SCR to issue the
REFA (auto-refresh) command to perform concentrated refresh on all memory rows ((REFA)
(REFA) (REFA)). The STR settings do not establish a relationship between the timing of the
PREALL and REFA commands that are issued by using SCR. A period of waiting that is
suitable for the memory unit must be inserted by software. At that time, if concentrated refresh
is necessary, execute the REFA command.
(In this case, the DCE bit should remain at 1.)
low. The DDR-SDRAM then automatically enters the power-down mode.
Self-Refresh Mode
DDR-SDRAM Access Mode
Power-Down Modes
Section 12 DDR-SDRAM Interface (DDRIF)
Rev. 1.00 Oct. 01, 2007 Page 433 of 1956
REJ09B0256-0100