r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 119

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

For the 64-bit data format, see figure 2.5.
2.6
This LSI has major three processing states: the reset state, instruction execution state, and power-
down state.
(1)
In this state the CPU is reset. The reset state is divided into the power-on reset state and the
manual reset.
In the power-on reset state, the internal state of the CPU and the on-chip peripheral module
registers are initialized. In the manual reset state, the internal state of the CPU and some registers
of on-chip peripheral modules are initialized. For details, see register descriptions for each section.
(2)
In this state, the CPU executes program instructions in sequence. The Instruction execution state
has the normal program execution state and the exception handling state.
(3)
In a power-down state, CPU halts operation and power consumption is reduced. The power-down
state is entered by executing a SLEEP instruction. There are two modes in the power-down state:
sleep mode and standby mode.
Reset State
Instruction Execution State
Power-Down State
Processing States
Address A + 4
Address A + 8
Address A
7
31
15
31
Byte 0
A
Word 0
0 7
23
Figure 2.7 Data Formats in Memory
Byte 1 Byte 2 Byte 3
A + 1
Big endian
Longword
0 7
0 15
15
A + 2
Word 1
0 7
7
A + 3
0
0
0
0
7
31
31
15
A + 11
Byte 3
Word 1
0 7
23
A + 10 A + 9
Byte 2 Byte 1 Byte 0
Little endian
Longword
Rev. 1.00 Oct. 01, 2007 Page 53 of 1956
0 7
0
15
15
Word 0
0 7
7
Section 2 Programming Model
A + 8
0
0
0
0
Address A + 8
Address A + 4
Address A
REJ09B0256-0100