r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 982

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.75 E-MAC/E-DMAC Status Interrupt Permission Register (EESIPR)
EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual
bits in the E-MAC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the
corresponding bit.
Rev. 1.00 Oct. 01, 2007 Page 916 of 1956
REJ09B0256-0100
Bit
31
30
29
28
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
TWB1
Bit Name
TWB1IP
TWB0IP
TC1IP
TUCIP
R/W
31
15
IP

R
0
0
TWB0
R/W
30
14
IP

R
0
0
R/W
TC1
29
13
IP

R
0
0
Initial
Value
0
0
0
0
R/W
TUC
28
12
IP

R
0
0
R/W
ROC
27
11

IP
R
0
0
R/W
R/W
R/W
R/W
R/W
TABT
R/W
R/W
DLC
26
10
IP
IP
0
0
Description
Write-Back Complete Interrupt Enable
0: Write-back complete interrupt is disabled
1: Write-back complete interrupt is enabled
Write-Back Complete Interrupt Enable
0: Write-back complete interrupt is disabled
1: Write-back complete interrupt is enabled
Frame Transmission Complete Interrupt Enable
0: Frame transmission complete interrupt is disabled
1: Frame transmission complete interrupt is enabled
Transmit Underflow Frame Write-Back Complete
Interrupt Enable
0: Transmit underflow frame write-back complete
1: Transmit underflow frame write-back complete
RABT
R/W
R/W
25
CD
IP
IP
0
9
0
interrupt is disabled
interrupt is enabled
RFCOF
R/W
R/W
TRO
24
IP
IP
0
8
0
RMAF
R/W
23

R
IP
0
7
0
CEEF
R/W
R/W
ECI
22
IP
IP
0
6
0
CELF
R/W
R/W
TC0
21
IP
IP
0
5
0
R/W
R/W
TDE
RRF
20
IP
IP
0
4
0
TFUF
RTLF
R/W
R/W
19
IP
IP
0
3
0
RTSF
R/W
R/W
18
FR
IP
IP
0
2
0
R/W
RDE
PRE
17
IP
IP
0
1
0
CERF
R/W
R/W
RFE
16
IP
IP
0
0
0