r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 24

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 24 IP Security Accelerator (SECURITY) ........................................... 995
Section 25 Stream Interface (STIF)................................................................... 997
25.1 Features.............................................................................................................................. 997
25.2 Input/Output Pins............................................................................................................... 999
25.3 Register Descriptions....................................................................................................... 1000
Section 26 I
26.1 Features............................................................................................................................ 1025
26.2 Input/Output Pins............................................................................................................. 1026
26.3 Register Descriptions....................................................................................................... 1026
26.4 Operations........................................................................................................................ 1044
Rev. 1.00 Oct. 01, 2007 Page xxiv of lxvi
25.3.1 Mode Registers 0, 1 (STIMDR0, STIMDR1)..................................................... 1002
25.3.2 Control Registers 0, 1 (STICR0, STICR1) ......................................................... 1006
25.3.3 Interrupt Status Registers 0, 1 (STIISR0, STIISR1) ........................................... 1007
25.3.4 Interrupt Enable Registers 0, 1 (STIIER0, STIIER1) ......................................... 1009
25.3.5 Time Stamp Counter Registers 0, 1 (STITSC0, STITSC1) ................................ 1011
25.3.6 Transmit/Receive Packet Count Registers 0, 1 (STIPNR0, STIPNR1) .............. 1012
25.3.7 Transmit/Receive Packet Counter Registers 0, 1 (STIPCR0, STIPCR1) ........... 1013
25.3.8 Transmit/Receive FIFO Data Registers 0, 1 (STIFIFO0, STIFIFO1) ................ 1014
25.3.9 Operation ............................................................................................................ 1015
25.3.10 External Memory Configuration for Stream Data Transmission/Reception....... 1015
25.3.11 Stream Data Receive Operation.......................................................................... 1016
25.3.12 Stream Data Transmit Operation ........................................................................ 1020
26.3.1 Slave Control Register (ICSCR)......................................................................... 1029
26.3.2 Slave Status Register (ICSSR)............................................................................ 1031
26.3.3 Slave Interrupt Enable Register (ICSIER) .......................................................... 1034
26.3.4 Slave Address Register (ICSAR)........................................................................ 1035
26.3.5 Master Control Register (ICMCR) ..................................................................... 1036
26.3.6 Master Status Register (ICMSR) ........................................................................ 1038
26.3.7 Master Interrupt Enable Register (ICMIER) ...................................................... 1040
26.3.8 Master Address Register (ICMAR) .................................................................... 1041
26.3.9 Clock Control Register (ICCCR)........................................................................ 1041
26.3.10 Receive and Transmit Data Registers (ICRXD and ICTXD) ............................. 1043
26.4.1 Data and Clock Filters ........................................................................................ 1044
26.4.2 Clock Generator.................................................................................................. 1044
26.4.3 Master/Slave Interfaces....................................................................................... 1044
26.4.4 Software Status Interlocking............................................................................... 1044
26.4.5 I
26.4.6 7-Bit Address Format.......................................................................................... 1047
2
2
C Bus Data Format ........................................................................................... 1046
C Bus Interface (IIC)................................................................... 1025