r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1068

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 25 Stream Interface (STIF)
25.3.1
STIMDR sets the STIF operating mode and clock definition for stream data
transmission/reception.
Initial value:
Initial value:
Rev. 1.00 Oct. 01, 2007 Page 1002 of 1956
REJ09B0256-0100
Bit
31
30 to 28 MD[2:0]
27 to 25 
24
23, 22
R/W:
R/W:
Bit:
Bit:
Bit Name

PLEN

Mode Registers 0, 1 (STIMDR0, STIMDR1)
CKSL
R/W
−
31
15
R
0
0
R/W
30
14
−
R
0
0
MD[2:0]
Initial
Value
0
000
All 0
0
All 0
R/W
R/W
CKDV[1:0]
29
13
0
0
R/W
R/W
28
12
0
0
R/W
R
R/W
R
R/W
R
27
11
−
−
R
R
0
0
26
10
−
−
R
R
0
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Stream Data Transfer Interface
000: Clock valid reception
010: Strobe reception
100: Clock valid transmission
101: Strobe transmission
Other than above: Setting prohibited
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit/Receive Packet Length
Sets the packet length of the stream data to be
transmitted or received.
0: Packet length is 188 bytes
1: Packet length is 192 bytes
Reserved
These bits are always read as 0. The write value should
always be 0.
25
−
−
R
R
0
9
0
PLEN
R/W
REQ
R/W
EN
24
0
8
0
23
−
−
R
R
0
7
0
22
−
−
R
R
0
6
0
R/W
R/W
STMP[1:0]
21
0
5
FRC[1:0]
0
R/W
R/W
20
0
4
0
STRB
R/W
19
−
R
0
3
0
REQ
R/W
18
−
R
0
2
0
R/W
WORK[1:0]
VLD
17
0
1
0
STAT
R/W
R/W
16
0
0
0