r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 44

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Figure 14.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 610
Figure 14.15 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 611
Figure 14.16 Example of DREQ Input Detection in Burst Mode Level Detection .................... 611
Figure 14.17 DMA Transfer End Signal (Cycle Steal Mode Level Detection) .......................... 612
Figure 14.18 Example of BSC Ordinary Memory Access
Section 15 External CPU Interface (EXCPU)
Figure 15.1 EXCPU Block Diagram .......................................................................................... 621
Figure 15.2 External CPU Access (Single Access) .................................................................... 630
Figure 15.3 External CPU Access (Burst Access)...................................................................... 631
Figure 15.4 Configuration of Connection with External CPU.................................................... 632
Section 16 Clock Pulse Generator (CPG)
Figure 16.1 Block Diagram of CPG ........................................................................................... 634
Figure 16.2 Notes on Using Crystal Resonator .......................................................................... 642
Figure 16.3 Notes on Using PLL or DLL Oscillator Circuit ...................................................... 643
Section 17 Watchdog Timer and Reset (WDT)
Figure 17.1 System Block Diagram............................................................................................ 646
Figure 17.2 WDT Counting Up Operation ................................................................................. 657
Figure 17.3 STATUS Output during Power-on.......................................................................... 660
Figure 17.4 STATUS Output by Reset input during Normal Operation .................................... 661
Figure 17.5 STATUS Output by Reset input during Sleep Mode .............................................. 661
Figure 17.6 STATUS Output by Watchdog timer overflow Power-On Reset during
Figure 17.7 STATUS Output by Watchdog timer overflow Power-On Reset
Figure 17.8 STATUS Output by Watchdog timer overflow Manual Reset during Normal
Figure 17.9 STATUS Output by Watchdog timer overflow Manual Reset during Sleep
Section 18 Power-Down Mode
Figure 18.1 DDR-SDRAM Interface Operation when Turning System Power Supply
Figure 18.2 Sequence for Turning Off System Power Supply after Entering Self-Refresh
Figure 18.3 Sequence for Turning VDD Power Supply (1.2 V) On/Off .................................... 685
Figure 18.4 STATUS Output when an Interrupt Occurs in Sleep Mode .................................... 685
Rev. 1.00 Oct. 01, 2007 Page xliv of lxvi
Normal Operation.................................................................................................... 662
during Sleep Mode .................................................................................................. 663
Operation................................................................................................................. 664
Mode ....................................................................................................................... 665
On/Off ..................................................................................................................... 682
Mode ....................................................................................................................... 683
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)............................... 613