r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 933

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

23.3.44 Added Qtag Value Set Register (Port 0 to 1) (TSU_ADQT0)
TSU_ADQT0 sets the Qtag data to be added in the conversion of normal Ethernet frames (no
Qtag) to IEEE802.1Q frames (with Qtag) in port 0 to 1 relay operations (if bits QTAG0[2:0] in
TSU_QTAG0 are set to H'3 or H'7 when using the Qtag adding function). This register must not
be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0
or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit
31 to 16
15 to 13
12
11 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
QTAG0[31:16] H'8100 R/W Be sure to set the value of the upper 16 bits
QTAG0[15:13] H'0

QTAG0[11:0]
R/W
R/W
31
15
1
0
QTAG0[15:13]
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
0
H'000
R/W
28
12

R
0
0
R/W
R/W
27
11
0
0
R/W Description
R/W Priority Setting (PRT)
R
R/W V-LAN ID Setting (VID)
R/W
R/W
26
10
0
0
(QTAG0[31:16]) as H'8100 (indicates the Qtag
extension frame format is used). The value read is
H'8100.
These bits set the processing priority of frames with
Qtag. For details on the settings, refer to the
specifications on Qtag control specified in IEEE802.1Q.
Reserved
This bit is always read as 0. The write value should
always be 0.
These bits should be set when frames with Qtag are to
be used in systems supporting V-LAN. For details on
settings, refer to the specifications on Qtag control
specified in IEEE802.1Q.
R/W
R/W
25
0
9
0
QTAG0[31:16]
R/W
R/W
24
1
8
0
Section 23 Gigabit Ethernet Controller (GETHER)
R/W
R/W
23
0
7
0
QTAG0[11:0]
R/W
R/W
Rev. 1.00 Oct. 01, 2007 Page 867 of 1956
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
REJ09B0256-0100
R/W
R/W
18
0
2
0
R/W
17
0
1
0
R/W
R/W
16
0
0
0