r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1282

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r5s77631ay266bgv

Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 29 Serial I/O with FIFO (SIOF)
Rev. 1.00 Oct. 01, 2007 Page 1216 of 1956
REJ09B0256-0100
Bit
11 to 8
7
6 to 4
3 to 0
Bit Name
CD0A[3:0]
CD1E
CD1A[3:0]
Initial
Value
0000
0
All 0
0000
R/W
R/W
R/W
R
R/W
Description
Control Channel 0 Data Assigns 3 to 0
Specify the position of control channel 0 data in a
receive or transmit frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
Control Channel 1 Data Enable
0: Disables transmission and reception of control
1: Enables transmission and reception of control
Reserved
These bits are always read as 0. The write value
should always be 0.
Control Channel 1 Data Assigns 3 to 0
Specify the position of control channel 1 data in a
receive or transmit frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
channel 1 data
channel 1 data
Transmit data for the control channel 0 data is
specified in the SITD0 bit in SITCR.
Receive data for the control channel 0 data is
stored in the SIRD0 bit in SIRCR.
Transmit data for the control channel 1 data is
specified in the SITD1 bit in SITCR.
Receive data for the control channel 1 data is
stored in the SIRD1 bit in SIRCR.

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