r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 126

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 3 Instruction Set
Rev. 1.00 Oct. 01, 2007 Page 60 of 1956
REJ09B0256-0100
Addressing
Mode
Register
indirect
with pre-
decrement
Register
indirect with
displacement
Indexed
register
indirect
Instruction
Format
@–Rn
@(disp:4, Rn) Effective address is register Rn contents with
@(R0, Rn)
Effective Address Calculation Method
Effective address is register Rn contents,
decremented by a constant beforehand:
1 for a byte operand, 2 for a word operand,
4 for a longword operand, 8 for a quadword
operand.
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the operand
size.
Effective address is sum of register Rn and R0
contents.
(zero-extended)
1/2/4/8
1/2/4
Rn
disp
Rn
R0
Rn
Rn – 1/2/4/8
×
–
+
+
Rn + disp × 1/2/4
Rn – 1/2/4/8
Rn + R0
Calculation
Formula
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
Quadword:
Rn – 8 → Rn
Rn → EA
(Instruction
executed
with Rn after
calculation)
Byte: Rn + disp
→ EA
Word: Rn + disp
× 2 → EA
Longword:
Rn + disp × 4 →
EA
Rn + R0 → EA