r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1230

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
In serial reception, the SCIF operates as described below.
1. The SCIF monitors the transmission line, and if a 0-start bit is detected, performs internal
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-
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synchronization and starts reception.
After receiving these bits, the SCIF carries out the following checks.
(a) Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
(b) The SCIF checks whether receive data can be transferred from SCRSR to SCFRDR.*
(c) Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun
(d) Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
data-full interrupt (RXI) request is generated.
If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
If the RIE bit or REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a
break reception interrupt (BRI) request is generated.
Note: *
the first is checked.
error has occurred.*
set.*
If (b), (c), and (d) checks are passed, the receive data is stored in SCFRDR.
Reception continues even when a parity error or framing error occurs.