r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 270

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Caches
7.5
7.5.1
Coherency between cache and external memory should be assured by software. In this LSI, the
following six instructions are supported for cache operations. Details of these instructions are
given in the Programming Manual.
• Operand cache invalidate instruction: OCBI @Rn
• Operand cache purge instruction: OCBP @Rn
• Operand cache write-back instruction: OCBWB @Rn
• Operand cache allocate instruction: MOVCA.L R0,@Rn
• Instruction cache invalidate instruction: ICBI @Rn
• Operand access synchronization instruction: SYNCO
The operand cache can receive "PURGE" and "FLUSH" transaction from SuperHyway bus to
control the cache coherency. Since the address used by the PURGE and FLUSH transaction is a
physical address, the following restrictions occur to avoid cache synonym problem in MMU
enable mode.
• 1 Kbyte page size cannot be used.
Rev. 1.00 Oct. 01, 2007 Page 204 of 1956
REJ09B0256-0100
Operand cache invalidation (no write-back)
Operand cache invalidation (with write-back)
Operand cache write-back
Operand cache allocation
Instruction cache invalidation
Wait for data transfer completion
Cache Operation Instruction
Coherency between Cache and External Memory