r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1122

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 26 I
(4)
1. Wait for master event, bit MDR in the master status register.
2. Read data from the received data register.
3. Set the master control register to H'8A
4. Reset the MDR bit.
(5)
1. Handle the receive interrupt (MDR) in the last byte: that is, read the data and clear the MDR.
2. Wait for master event, MST in the master status register.
3. Reset the MST bit.
26.5.3
In order to set up the master interface to transmit a data packet on the I
read byte data back from the slave, follow the following procedure:
(1)
1. Set the SCL clock generation divider (SCGD) to H'03
2. Set the clock division (CDF) to H'2
(The peripheral clock is 66.7 MHz and the IIC's internal clock IICck is 16.7 MHz.)
(2)
1. Set the master address register to address of slave being accessed and STM1 bit (writes mode:
2. Set the master control register to H'89
(3)
1. Wait for master event (an interrupt of the MAT and MDE bits in the master status register).
Rev. 1.00 Oct. 01, 2007 Page 1056 of 1956
REJ09B0256-0100
If the next byte of data is the second to last byte to be transmitted by the slave device, the
following applies to the receive interrupt (that is, MDR interrupt) in the second to last byte.
(Set the force stop control bit).
(SCL frequency of 400 kHz).
0).
(MDBS = 1, MIE = 1, ESG = 1).
Monitor Reception of Data
Wait for End of Reception
Load Clock Control Register
Load Master Control Register and Address
Wait for Outputting Address
Master Transmitter—Restart—Master Receiver
2
C Bus Interface (IIC)
2
C bus, issue a restart, then