r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 705

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

16.4.1
FRQCR is a 32-bit read-only register used to confirm the division ratios for the CPU clock (Ick),
SHwy clock (SHck), peripheral clocks (Pck0, Pck1), and the bus clock (Bck) after a power-on
reset. For the frequency ratios, refer to table 16.2, Clock Operating Modes. This register can be
accessed only in longwords. Operation cannot be guaranteed if this register is written to.
FRQCR is only initialized by a power-on reset caused by the PRESET pin or watchdog timer
overflow.
Initial value:
Initial value:
Bit
31 to 28
27 to 23
22 to 20
19
18 to 16
15 to 7
6 to 4
R/W:
R/W:
Bit:
Bit:
Frequency Control Register (FRQCR)
Bit Name
—
—
—
—
P0FC[2:0]
CFC[2:0]
BFC[2:0]

31
15

R
R
0
0


30
14
0
R
R
0
29

13

R
R
0
0
Initial
Value
0001
All 0
001
0
011
All 0
011
R/W
R/W
28
12


1
0
R/W
R/W
27
11
R/W
R
R
R
R
R
R
R


0
0
R/W
R/W
26

10

0
0
Description
Reserved
These bits are read as B'0001.
Reserved
These bits are always read as all 0.
CPU Clock (Ick) and SHwy Clock (SHck) Frequency
Division Ratios
Reserved
This bit is always read as 0.
Bus Clock 0 (Bck) Frequency Division Ratio
011: ×1/8
Reserved
These bits are always read as all 0.
Peripheral Clock 0 (Pck0) Frequency Division Ratio
011: ×1/8
CFC[2:0]
001:
R/W
R/W
25


0
0
9
R/W
R/W
24


0
8
0
23


Ick
×1/2
R
R
0
7
0
Rev. 1.00 Oct. 01, 2007 Page 639 of 1956
Section 16 Clock Pulse Generator (CPG)
22
R
R
0
6
0
SHck
×1/4
P0FC[2:0]
CFC[2:0]
21
0
R
5
1
R
R/W
R/W
20
4
1
1
R/W
R/W
19


3
0
0
REJ09B0256-0100
R/W
R/W
18
2
0
1
P1FC[2:0]
BFC[2:0]
R/W
R/W
17
1
1
0
R/W
R/W
16
1
0
1