r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1474

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 33 Audio Codec Interface (HAC)
Rev. 1.00 Oct. 01, 2007 Page 1408 of 1956
REJ09B0256-0100
Bit
29
28, 27
26
25
24
23
22
21
20 to 0
Bit Name
DMATX16

TX12_ATOMIC

RXDMAL_EN
TXDMAL_EN
RXDMAR_EN
TXDMAR_EN

Initial
Value
0
All 0
1
0
0
0
0
0
All 0
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R
Description
16-bit TX DMA Enable
0: Disables 16-bit packed TX DMA mode. Enables the
1: Enables 16-bit packed TX DMA mode. Disables the
Reserved
Always 0 for read and write.
TX Slot 1 and 2 Atomic Control
0: Transmits TX data in HACCSAR and that in
1: Transmits TX data in HACCSAR and that in
Reserved
Always 0 for read and write.
RX DMA Left Enable
0: Disables 20-bit RX DMA for HACPCML.
1: Enables 20-bit RX DMA is for HACPCML.
TX DMA Left Enable
0: Disables 20-bit TX DMA for HACPCML.
1: Enables 20-bit TX DMA for HACPCML.
RX DMA Right Enable
0: Disables 20-bit RX DMA for HACPCMR.
1: Enables 20-bit RX DMA for HACPCMR.
TX DMA Right Enable
0: Disables 20-bit TX DMA for HACPCMR.
1: Enables 20-bit TX DMA for HACPCMR.
Reserved
Always 0 for read and write.
TXDMAL_EN and TXDMAR_EN settings.
TXDMAL_EN and TXDMAR_EN settings.
HACCSDR separately. (Setting prohibited)
HACCSDR in the same frame if bit 19 in HACCSAR
is 0 (write). (HACCSAR must be written last.)