r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 673

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

(SAR, DAR, TCR, CHCR, DMAOR,
TCR – 1 → TCR, SAR, and DAR updated
SARB, DARB, TCRB, DMARS)
Reload mode: TCR[7:0] → TCRBL
Notes: 1. In repeat mode, a transfer request is acceptted with TE =1 when HIE = 1 and HE = 0
Transfer request occurs?
Transfer (1 transfer unit);
DEI interrupt request
NMIF = 1 or AE =1 or
DE = 0 or DME = 0?
TE, AE, NMIF = 0?
DE, DME = 1 and
Reload mode?
Repeat mode?
Initial settings
Normal end
Yes
Yes
2. In auto-request mode, transfer starts when bits NMIF, AE, and TE are all 0 or bits TE
3. DREQ is level detection (external requesrt) in burst mode or cycle-steral mode.
4. DREQ is edge detection (external request) or auto request in burst mode.
5. Loading to SAR and DAR differs according to the operating conditions in each mode.
TCR = 0?
Yes
No
No
No
(IE = 1)
TE = 1
Start
(half end interrupt is enable and clear the HE to 0 after HE is set to 1).
and HIE are 1 and HE is 0 (in repeat mode), and bits DE and DME are set to 1.
*
*
1
2
Figure 14.11 DMA Transfer Flowchart
Yes
No
Yes
No
Yes
No
No
TCR[23:16] → TCR[7:0] load
*
6
SARB/DARB load
TCRB → TCR load
HIE = 0 or HE = 1?
SARB/DARB load
TCR[7:0] = 0?
Yes
Yes
Section 14 Direct Memory Access Controller (DMAC)
*
*
No
*
5
6
5
No
HE = 1, DEI interrupt
NMIF = 1 or AE = 1 or
request (HIE = 1)
TCR = TCRB/2?
DE = 0 or DME = 0?
Transfer end
Rev. 1.00 Oct. 01, 2007 Page 607 of 1956
Yes
Yes
*
4
transfer request mode
Bus mode, DREQ
detection system,
No
*
REJ09B0256-0100
3