r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1074

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 25 Stream Interface (STIF)
Note:
Rev. 1.00 Oct. 01, 2007 Page 1008 of 1956
REJ09B0256-0100
Bit
11, 10
9
8
7 to 5
4
3 to 1
0
*
Bit Name

LONG
SHORT

ROVF

TSTO
Write 1 to clear the bit.
Initial
Value
All 0
0
0
All 0
0
All 0
0
R/W
R
R/W* Long Packet Reception Interrupt
R/W* Short Packet Reception Interrupt
R
R/W* Receive FIFO Overflow Interrupt
R
R/W* Time Stamp Counter Overflow Interrupt
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
0: Packet exceeding 188 or 192 bytes has not been
1: Packet exceeding 188 or 192 bytes has been received
When a packet exceeding 188 or 192 bytes is received,
the long packet counter and packet counter are both
incremented by one.
Data of 188 or 192 bytes is transferred to memory and
the excess data is discarded.
0: Packet less than 188 or 192 bytes has not been not
1: Packet less than 188 or 192 bytes has been received
When a packet less than 188 or 192 bytes is received,
the short packet counter is incremented by one and the
packet is discarded.
Reserved
These bits are always read as 0. The write value should
always be 0.
0: Receive FIFO has not overflowed
1: Receive FIFO has overflowed
The packets already received are retained, but the
packet that caused overflow is discarded.
Reserved
These bits are always read as 0. The write value should
always be 0.
0: Time stamp counter has not cycled once after
1: Time stamp counter has cycled once after receiving
received
received
receiving the last packet.
the last packet.