r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 121

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

2.7
2.7.1
This LSI prefetches instructions more drastically than conventional SH-4 to accelerate the
processing speed. Therefore if the instruction in the memory is modified and it is executed
immediately, then the pre-modified code that is prefetched are likely to be executed. In order to
execute the modified code definitely, one of the following sequences should be executed between
the execution of modifying codes and modified codes.
(1)
(2)
(3)
The all operand cache area corresponding to the modified codes should be written back to the
main memory by the OCBP or OCBWB instruction. Then the all instruction cache area
corresponding to the modified codes should be invalidated by the ICBI instruction. The OCBP,
OCBWB and ICBI instruction should be issued to each cache line. One cache line is 32 bytes.
Note: * Processes executed while changing the instructions on the memory dynamically.
SYNCO
ICBI
The target for the ICBI instruction can be any address within the range where no address error
exception occurs.
SYNCO
ICBI
The all instruction cache area corresponding to the modified codes should be invalidated by the
ICBI instruction. The ICBI instruction should be issued to each cache line. One cache line is 32
bytes.
OCBP @Rm or OCBWB @Rm
SYNCO
ICBI
In case the modified codes are in non-cacheable area
In case the modified codes are in cacheable area (write-through)
In case the modified codes are in cacheable area (copy-back)
Usage Note
Notes on Self-Modified Codes*
@Rn
@Rn
@Rn
Rev. 1.00 Oct. 01, 2007 Page 55 of 1956
Section 2 Programming Model
REJ09B0256-0100