r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 821

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

21.3
21.3.1
The CMT starts the operation of the counter by writing a 1 to the STRn bit in CMSTR of a
channel that has been selected for operation. Complete all of the settings before starting the
operation. Do not change the register settings other than by clearing flag bits.
The counter operates in one of two ways.
• One-Shot Operation
• Free-Running Operation
One-shot operation is selected by setting the CMM bit in CMCSR to 0. When the value in
CMCNT matches the value in CMCOR, the value in CMCNT is cleared to H'00000000 and
the CMF bit in CMCSR is set to 1. Counting by CMCNT stops after it has been cleared.
To detect an overflow interrupt, set the value in CMCOR to H'FFFFFFFF. When the value in
CMCNT matches the value in CMCOR, CMCNT is cleared to H'00000000 and bits CMF and
OVF in CMCSR are set to 1.
Free-running operation is selected by setting the CMM bit in CMCSR to 1. When the value in
CMCNT matches the value in CMCOR, CMCNT is cleared to H'00000000 and the CMF bit in
CMCSR is set to 1. CMCNT resumes counting-up after it has been cleared.
To detect an overflow interrupt, set CMCOR to H'FFFFFFFF. When the values in CMCNT
and CMCOR match, CMCNT is cleared to H'00000000 and bits CMF and OVF in CMCSR
are set to 1.
H'00000000
CMCOR
Value in
CMCNT
Operation
Counter Operation
Figure 21.2 Counter Operation (One-Shot Operation)
CMF = 1
OVF = 1 (When an overflow is detected)
Rev. 1.00 Oct. 01, 2007 Page 755 of 1956
Section 21 Compare Match Timer (CMT)
REJ09B0256-0100
Time