r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 59

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Table 11.15
Section 12 DDR-SDRAM Interface (DDRIF)
Table 12.1
Table 12.2
Table 12.3
Table 12.4
Table 12.5
Table 12.6
Table 12.7
Section 13 PCI Controller (PCIC)
Table 13.1
Table 13.2
Table 13.3
Table 13.4
Table 13.5
Table 13.6
Section 14 Direct Memory Access Controller (DMAC)
Table 14.1
Table 14.2
Table 14.3
Table 14.4
Table 14.5
Table 14.6
Table 14.7
Table 14.8
Table 14.9
Table 14.10
Table 14.11
Table 14.12
Table 14.13
Table 14.14
Table 14 15
Section 15 External CPU Interface (EXCPU)
Table 15.1
Table 15.2
Table 15.3
Pin Configuration.................................................................................................... 81
Access and Data Alignment in Little Endian Mode
(External Bus Width is 32 Bits) .............................................................................. 82
Access and Data Alignment in Big Endian Mode
(External Bus Width is 32 Bits) .............................................................................. 83
Register Configuration............................................................................................ 85
Register State in Each Operating Mode .................................................................. 86
DDR-SDRAM Commands Issued by DDRIF ...................................................... 102
DDR-SDRAM Address Multiplexing (32-Bit Data Bus) ..................................... 106
Input/Output Pins.................................................................................................... 82
List of PCIC Registers ............................................................................................ 85
Register States in Each Operating Mode ................................................................ 88
Supported Bus Commands.................................................................................... 157
PCIC Address Map ............................................................................................... 159
Interrupt Priority ................................................................................................... 178
Pin Configuration.................................................................................................... 81
Register Configuration of DMAC........................................................................... 83
State of Registers in Each Operating Mode ............................................................ 85
Transfer Request Sources ..................................................................................... 103
Setting External Request Mode with RS bit ......................................................... 105
Selecting External Request Detection with DL, DS Bits ...................................... 106
Selecting External Request Detection with DO Bit .............................................. 106
Selecting On-Chip Peripheral Module Request Modes with Bits RS[3:0] ........... 107
DMA Transfer Matrix in Auto-Request Mode (all channels)............................... 117
Pin Configuration.................................................................................................. 612
Register Configuration.......................................................................................... 613
Register States in Each Operating Mode .............................................................. 613
Relationship between Address and CE When Using PCMCIA Interface ......... 380
DMA Transfer Matrix in External Request Mode (only channels 0 to 3)......... 118
DMA Transfer Matrix in On-Chip Peripheral module Request Mode.............. 119
Register Setting for SRAM, Burst ROM, Byte Control SRAM Interface. ....... 131
Register Setting for PCMCIA Interface............................................................ 132
Register Setting for MPX Interface (Read Access) .......................................... 132
Register Settings for MPX Interface (Write Access) ........................................ 132
Rev. 1.00 Oct. 01, 2007 Page lix of lxvi