r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 220

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 Memory Management Unit (MMU)
Initial value:
Initial value:
Rev. 1.00 Oct. 01, 2007 Page 154 of 1956
REJ09B0256-0100
Bit
31 to 5
4
3
2
1
R/W:
R/W:
Bit:
Bit:
Bit Name

R2
R1
LT
MT
31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
Initial
Value
All 0
0
0
0
0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R/W
R/W
R/W
R/W
26
10
R
R
0
0
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
Re-Fetch Inhibit 2 after Register Change
When MMUCR, PASCR, CCR, PTEH, or RAMCR is
changed, this bit controls whether re-fetch is
performed for the next instruction.
0: Re-fetch is performed
1: Re-fetch is not performed
Re-Fetch Inhibit 1 after Register Change
When a register allocated in addresses H'FF200000 to
H'FF2FFFFF is changed, this bit controls whether re-
fetch is performed for the next instruction.
0: Re-fetch is performed
1: Re-fetch is not performed
Re-Fetch Inhibit after LDTLB Execution
This bit controls whether re-fetch is performed for the
next instruction after the LDTLB instruction has been
executed.
0: Re-fetch is performed
1: Re-fetch is not performed
Re-Fetch Inhibit after Writing Memory-Mapped TLB
This bit controls whether re-fetch is performed for the
next instruction after writing memory-mapped
ITLB/UTLB while the AT bit in MMUCR is set to 1.
0: Re-fetch is performed
1: Re-fetch is not performed
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
R/W
R2
20
R
0
4
0
R/W
R1
19
R
0
3
0
R/W
18
LT
R
0
2
0
R/W
MT
17
R
0
1
0
R/W
MC
16
R
0
0
0