r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 334

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 9 Interrupt Controller (INTC)
9.3.14
INT2A0 (mask state is not affected) is a 32-bit read-only register that indicates interrupt source
modules. Even if interrupt masking is set in the interrupt mask register, INT2A0 indicates a source
module in a corresponding bit (the corresponding interrupt is not generated). If source indication is
not necessary depending on the state of the interrupt mask register, use INT2A1.
Initial value:
Initial value:
Rev. 1.00 Oct. 01, 2007 Page 268 of 1956
REJ09B0256-0100
Bit
31 to 26 —
25
24
23
22
21
20
19
18
17
16
15
14
13
R/W:
R/W:
Bit:
Bit:
Interrupt Source Register 0 (Mask State is not affected) (INT2A0)
Bit Name
GPIO
—
SSI0
MMCIF
—
SIOF0
PCIC5
PCIC4
PCIC3
PCIC2
PCIC1
PCIC0
HAC
PCIC1 PCIC0 HAC CMT
−
31
15
R
R
0
0
−
30
14
R
R
0
0
Initial
Value
All 0
0
0
0
0
0
0
0
0
0
0
0
0
0
−
29
13
R
R
0
0
28
12
−
R
R
0
0
R
R
R
R
R/W
R
R
R
R
R
R
R
R
R
R
27
11
−
−
R
R
0
0
26
10
−
−
R
R
0
0
Function
These bits are always read as 0.
The write value should always be
0.
Indicates GPIO interrupt source
This bit is always read as 0. The
write value should always be 0.
Indicates SSI0 interrupt source
Indicates MMCIF interrupt source
This bit is always read as 0. The
write value should always be 0.
Indicates SIOF0 interrupt source
Indicates PCIC5 interrupt source
Indicates PCIC4 interrupt source
Indicates PCIC3 interrupt source
Indicates PCIC2 interrupt source
Indicates PCIC1 interrupt source
Indicates PCIC0 interrupt source
Indicates HAC interrupt source
GPIO
25
−
R
R
0
9
0
DMAC H-UDI
−
24
R
R
0
8
0
SSIO MMCIF
23
R
R
0
7
0
22
−
R
R
0
6
0
WDT SCIF1 SCIF0 RTC TMU1 TMU0
21
−
R
R
0
5
0
SIOF0 PCIC5 PCIC4 PCIC3 PCIC2
20
R
R
0
4
0
Description
Indicates interrupt
sources for each
peripheral module
(INT2A0 is not
affected by the state
of the interrupt mask
register).
0: No interrupts
1: Interrupts are
Note: Reading the
19
R
R
0
3
0
generated
INTEVT code
notified to the
CPU directly
can identify
interrupt
sources. In this
case, reading
INT2A0 is not
necessary.
18
R
R
0
2
0
17
R
R
0
1
0
16
R
R
0
0
0