r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 297

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

When the OCBWB instruction is issued to the L memory area, the physical address bits [28:10]
are generated in accordance with the LDA0 or LDA1 specification. The physical address bits [9:5]
are generated from the virtual address. The physical address bits [4:0] are fixed to 0. Block
transfer is performed from the L memory to the external memory specified by these physical
addresses.
8.4
This LSI implements the following protective functions to the L memory by using the on-chip
memory access mode bit (RMD) and the on-chip memory protection enable bit (RP) in the on-chip
memory control register (RAMCR).
• Protective functions for access from the CPU and FPU
The above descriptions are summarized in table 8.4.
Table 8.4
Note: * Don't care
MMUCR.AT RAMCR.RP SR.MD
0
1
When RAMCR.RMD = 0, and the L memory is accessed in user mode, it is determined to be
an address error exception.
When MMUCR.AT = 1 and RAMCR.RP = 1, MMU exception and address error exception are
checked in the L memory area which is a part of P4 area as with the area P0/P3/U0.
L Memory Protective Functions
Protective Function Exceptions to Access L Memory
*
0
1
0
1
0
1
0
1
RAMCR. RMD
0
1
*
0
1
*
0
1
*
Always Occurring
Exceptions
Address error
exception
—
—
Address error
exception
—
—
Address error
exception
—
—
Rev. 1.00 Oct. 01, 2007 Page 231 of 1956
Possibly Occurring
Exceptions
—
—
—
—
—
—
—
MMU exception
MMU exception
Section 8 L Memory
REJ09B0256-0100