r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1259

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Bit
7
6
5
4
3 to 0
Bit Name
TXDIZ
RCIM
SYNCAC
SYNCDL
—
Initial
Value
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R
Description
SIOF_TXD Pin Output when Transmission is Invalid*
0: High output (1 output) when invalid
1: High-impedance state when invalid
Note: Invalid means when disabled, and when a slot
Receive Control Data Interrupt Mode
0: Sets the RCRDY bit in SISTR when the contents of
1: Sets the RCRDY bit in SISTR each time when the
SIOF_SYNC Pin Polarity
Valid when the SIOF_SYNC signal is output as a
synchronous pulse.
0: Active-high
1: Active-low
Data Pin Bit Delay for SIOF_SYNC Pin
Valid when the SIOF_SYNC signal is output as
synchronous pulse. Only one-bit delay is valid for
transmission in slave mode. This bit should be set to 1.
0: No bit delay
1: 1-bit delay
Note: * When this bit is cleared to 0 (no bit delay is
Reserved
These bits are always read as 0. The write value should
always be 0.
SIRCR change.
SIRCR receives the control data.
that is not assigned as transmit data or control
data is being transmitted.
selected) in slave mode, the receive data is
sampled at the rising edge of SCK.
Rev. 1.00 Oct. 01, 2007 Page 1193 of 1956
Section 29 Serial I/O with FIFO (SIOF)
REJ09B0256-0100