r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1221

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

In asynchronous mode, a character that consists of data with a start bit indicating the start of

communication and a stop bit indicating the end of communication is transmitted or received. In

this mode, serial communication is performed with synchronization achieved character by

Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex

communication. Both the transmitter and receiver have a 16-stage FIFO buffer structure, so that

data can be read or written during transmission or reception, enabling continuous data

transmission and reception.

Figure 28.5 shows the general format for asynchronous serial communication.

In asynchronous serial communication, the transmission line is usually held in the mark state (high

level). The SCIF monitors the transmission line, and when it goes to the space state (low level),

recognizes a start bit and starts serial communication.

One character in serial communication consists of a start bit (low level), followed by

transmit/receive data (LSB-first; from the lowest bit), a parity bit (high or low level), and finally

stop bits (high level).

In reception in asynchronous mode, the SCIF synchronizes with the fall of the start bit. Receive

data can be latched at the middle of each bit because the SCIF samples data at the eighth clock

which has a frequency of 16 times the bit rate.

Operation in Asynchronous Mode

Figure 28.5 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, and Two Stop Bits)

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)

One unit of transfer data (character or frame)

Transmit/receive data

Rev. 1.00 Oct. 01, 2007 Page 1155 of 1956

(mark state)

REJ09B0256-0100