r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 347

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

9.3.21
INT2MSKCR1 is a 32-bit write-only register that clears any masking set in the interrupt mask
register. Setting bits in this register to 1 clears the masking of the corresponding interrupt sources.
Reading bits in this register is always 0.
Initial value:
Initial value:
Bit
7
6
5
4
3
2
1
0
R/W:
R/W:
Bit:
Bit:
Interrupt Mask Clear Register 1 (INT2MSKCR1)
Bit Name
H-UDI
—
WDT
SCIF1
SCIF0
RTC
TMU1
TMU0
PCC
R/W
Note: * This bit is reserved in the R5S77631.
31
−
15
R
0
0
30
14
−
−
R
R
0
0
Initial
Value
0
0
0
0
0
0
0
0
29
13
−
−
R
R
0
0
ADC
R/W
28
−
12
R
0
0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
TPU
R/W
27
−
11
R
0
0
R/W
SIM SIOF2 SIOF1 LCDC
26
10
−
R
0
0
Function
Clears H-UDI interrupt
masking
This bit is always read as 0.
The write value should always
be 0
Clears WDT interrupt masking
Clears SCIF1 interrupt
masking
Clears SCIF0 interrupt
masking
Clears RTC interrupt masking
Clears TMU1 interrupt
masking
Clears TMU0 interrupt
masking
SCIF2 USBF
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
R/W
23
−
R
0
7
0
Rev. 1.00 Oct. 01, 2007 Page 281 of 1956
22
−
R
−
R
0
6
0
Section 9 Interrupt Controller (INTC)
STIF1 STIF0
R/W
R/W
IIC1
21
0
5
0
IIC0
R/W
R/W
20
0
4
0
Description
Clears interrupt
masking for each
peripheral module.
[When writing]
0: Invalid
1: Interrupt mask is
[When reading]
Always 0
cleared
SSI3 SSI2
R/W
19
−
R
0
3
0
REJ09B0256-0100
R/W
18
−
R
0
2
0
USBH
SSI1
R/W
R/W
17
0
1
0
SECU
RITY*
GETH
R/W
R/W
16
ER
0
0
0