r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1500

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 34 Serial Sound Interface (SSI)
Rev. 1.00 Oct. 01, 2007 Page 1434 of 1956
REJ09B0256-0100
Bit
24
23 to 4
3, 2
Bit Name
DIRQ

CHNO[1:0] 00
Initial
Value
0
H'10A00 R
R/W
R
R
Description
Data Interrupt Status Flag
This status flag indicates that the SSI module requires
that data be either read out or written in.
This bit is set to 1 regardless of the setting of DIEN bit,
so that polling will be possible.
The interrupt can be masked by clearing DIEN bit to 0,
but writing 0 in this bit will not clear the interrupt.
If DIRQ = 1 and DIEN = 1, then an interrupt will be
generated.
When TRMD = 0 (Receive Mode):
0: No unread data exists in SSIRDR.
1: Unread data exists in SSIRDR.
When TRMD = 1 (Transmit Mode):
0: The transmit buffer is full.
1: The transmit buffer is empty, and requires that data
Reserved
These bits are always read as H'10A00. The write value
should always be 0.
Channel Number
The number indicates the current channel.
When TRMD = 0 (Receive Mode):
This bit indicates to which channel the current data in
SSIRDR belongs. When the data in SSIRDR is updated
by transfer from the shift register, this value will change.
When TRMD = 1 (Transmit Mode):
This bit indicates the data of which channel should be
written in SSITDR. When data is copied to the shift
register, regardless whether the data is written in
SSITDR, this value will change.
be written in SSITDR.