r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 449
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r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
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Figures 11.18 and 11.19 show the timing for the PCMCIA I/O card interface.
When accessing a PCMCIA card via the I/O card interface, it is possible to perform dynamic
sizing of the I/O bus width using the IOIS16 pin. With the 16-bit bus width selected, if the IOIS16
signal is high during the word-size I/O bus cycle, the I/O port is recognized as eight bits in bus
width. In this case, a data access for only eight bits is performed in the I/O bus cycle being
executed, and this is automatically followed by a data access for the remaining eight bits. Dynamic
bus sizing is also performed for byte-size access to address 2n + 1.
Figure 11.20 shows the basic timing for dynamic bus sizing.
I/O Card Interface Timing
IOWR
(Write)
CLKOUT
A25 to A0
CExx
PCC_REG (WE0)
RDWR
IORD
(read)
D15 to D0
(read)
D15 to D0
(Write)
BS
DACK
(DA)
DA: Dual address DMA
Figure 11.18 Basic Timing for PCMCIA I/O Card Interface
T
pci1
Section 11 Local Bus State Controller (LBSC)
Rev. 1.00 Oct. 01, 2007 Page 383 of 1956
T
pci2
REJ09B0256-0100
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