r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 880

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.3
ECSR is a 32-bit readable/writable register that indicates the status in the E-MAC. This status can
be notified to the CPU by interrupts. When 1 is written to the PFROI, LCHNG, MPD, and ICD
bits, the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that
generate interrupts, the interrupt can be enabled or disabled by the corresponding bit in ECSIPR.
Writing 1 or 0 to the PHYI bit does not change its value.
The interrupts generated due to this status register are indicated in each ECI bit in EESR of the E-
DMAC0 for port 0 and the E-DMAC1 for port 1.
Rev. 1.00 Oct. 01, 2007 Page 814 of 1956
REJ09B0256-0100
Bit
31 to 5
4
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
E-MAC Status Register (ECSR)
Bit Name

PFROI
31
15


R
R
0
0
30
14


R
R
0
0
29
13


R
R
0
0
Initial
Value
All 0
0
28
12


R
R
0
0
27
11

R/W
R
R/W

R
R
0
0
26
10


R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
PAUSE Frame Retransmit Retry Over
Indicates whether the retransmit count for
retransmitting a PAUSE frame when flow control is
enabled has exceeded the retransmit upper-limit set in
the automatic PAUSE frame retransmit count register
(TPAUSER).
0: PAUSE frame retransmit count has not exceeded the
1: PAUSE frame retransmit count has exceeded the
25


R
R
0
9
0
upper limit
upper limit
24


R
R
0
8
0
23


R
R
0
7
0
22


R
R
0
6
0
21


R
R
0
5
0
PFROI
R/W
20

R
0
4
0
PHYI LCHNG MPD
19

R
R
0
3
0
R/W
18

R
0
2
0
17

R
0
1
0
R/W
ICD
16

R
0
0
0