r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 762

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 19 Timer Unit (TMU)
19.3.5
The TCR registers are 16-bit readable/writable registers. Each TCR selects the count clock,
specifies the edge when an external clock is selected, and controls interrupt generation when the
flag indicating TCNT underflow is set to 1. TCR2 is also used for input capture control and
control of interrupt generation in the event of input capture.
• TCR0, TCR1, TCR3, TCR4 and TCR5
• TCR2
Rev. 1.00 Oct. 01, 2007 Page 696 of 1956
REJ09B0256-0100
Initial value:
Initial value:
Bit
15 to 10 —
9
8
R/W:
R/W:
BIt:
BIt:
Timer Control Registers (TCRn) (n = 0 to 5)
Bit Name
ICPF*
UNF
15
15
—
—
R
R
0
0
1
14
14
—
—
R
R
0
0
13
13
—
—
R
R
0
0
Initial
Value
All 0
0
0
12
12
—
—
R
R
0
0
R/W
R
R/W
R/W
11
—
11
—
R
R
0
0
10
10
—
—
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Input Capture Interrupt Flag
Status flag, provided in channel 2 only, which indicates
the occurrence of input capture.
0: Input capture has not occurred
[Clearing condition]
When 0 is written to ICPF
1: Input capture has occurred
[Setting condition]
When input capture occurs*
Underflow Flag
Status flag that indicates the occurrence of TCNT
underflow.
0: TCNT has not underflowed
[Clearing condition]
When 0 is written to UNF
1: TCNT has underflowed
[Setting condition]
When TCNT underflows*
ICPF
R/W
—
R
0
0
9
9
UNF
UNF
R/W
R/W
8
0
8
0
ICPE1
R/W
—
R
7
0
7
0
ICPE0
R/W
—
R
6
0
6
0
UNIE
UNIE
R/W
R/W
5
0
5
0
2
2
CKEG1
CKEG1
R/W
R/W
4
0
4
0
CKEG0
CKEG0
R/W
R/W
3
0
3
0
TPSC2
TPSC2
R/W
R/W
2
0
2
0
TPSC1
TPSC1
R/W
R/W
1
0
1
0
TPSC0
TPSC0
R/W
R/W
0
0
0
0