r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1116

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 26 I
26.4.8
The transmit procedure and operation in master transmit mode are described below. Figure 26.9
shows the timing chart in master transmit mode. Setting the MDBS bit in the master control
register allows the IIC to operate in single-buffer mode.
1. For initial setting, set the clock control register and the master interrupt enable register
2. Monitor the FSDA bit in the master control register. Confirm that this bit is low, meaning that
3. After the transmit START condition, slave address, and data transfer direction bits are
4. An interrupt due to the SAR bit is generated at the timing of (3) shown in figure 26.9. If the
5. Data is transmitted in units of nine bits: 8-bit data and 1-bit ACK. An interrupt of MDE (bit 3)
6. To end data transfer, an interrupt of MNR (bit 6) in the master status register is generated at
7. The FSB bit needs to be set before the last byte data is transferred. In master transmit mode,
Rev. 1.00 Oct. 01, 2007 Page 1050 of 1956
REJ09B0256-0100
according to the slave address, transmit data, and the transmit speed. Since slave mode is also
required even when master mode is used, set the device address in the slave address register.
other I
bits in the master control register to 1 to start master transmission.
transmitted, an interrupt due to the MAT and MDE bits in the master status register is
generated at the timing of (1) in figure 26.9. At this time, clear the ESG bit to 0. To suspend
the data transmission, the master device will hold SCL low until the MDE bit is cleared.
IRQ handling in the slave device is delayed, the slave device extends the IIC_SCL period to
suspend data transmission (at the timing of (7) in figure 26.9). The slave device drives
IIC_SDA low at the ninth clock and returns ACK.
is generated at the ninth clock before data transfer (at the timing of (2) in figure 26.9). An
interrupt of MDT (bit 2) is generated at the eighth clock after 1-byte data transfer (at the timing
of (4) in figure 26.9). Clear MDE to 0 after setting transmit data. An interrupt of SDR (slave
data receive) of the slave device is generated at the eighth clock (at the timing of (6) in figure
26.9). Clear SDR after the slave device reads the receive data. If this processing is delayed, the
slave device extends the SCL period to suspend data transmit (at the timing of (8) in figure
26.9).
the ninth clock (at the timing of (5) in figure 26.9) when ACK from the slave device is 1
(Nack). The master device receives this Nack and outputs data transfer end condition. When
data transmission ends on the master device side, set FSB (bit 1) in the master control register
to 1 to output the suspend condition. After the IIC module fetches FSB on completion of
transmission or reception of the last of byte data, it enters the stop state. Therefore in order to
stop the communication after the predetermined number of byte data is transferred, the FSB bit
needs to be set before the last byte data transfer is started.
after the last byte data is set, the MST (master stop transmitted) bit is checked by either
Master Transmit Operation
2
C devices are not using the bus. After confirmation, set the MIE (bit 3) and ESG (bit 0)
2
C Bus Interface (IIC)