r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 332

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 9 Interrupt Controller (INTC)
UIMASK level are held disabled, and correct operation may not be performed (for example, the
OS cannot switch tasks).
An example of the usage procedure is shown below.
1. Classify interrupts to A and B as described below and set the A priority higher than the B
2. Make the MMU settings so that the address space including USERIMASK can only be
3. Branch to the device driver.
4. Set the UIMASK bit to mask B interrupts in the device driver that is operating in user mode.
5. Process interrupts with high priority in the device driver.
6. Clear the UIMASK bit to 0 to return from processing in the device driver.
9.3.13
INT2PRI0 to INT2PRI13 are 32-bit readable/writable registers that set priorities (levels 31 to 0) of
the on-chip peripheral module interrupts. INT2PRI0 to INT2PRI13 are initialized to H'0000 0000
by a reset.
INT2PRI0 to INT2PRI13 can set 30 priority levels (32 types of interrupt requests) to individual
interrupt sources with five bits (interrupt requests are masked at H'00 and H'01).
Initial value:
Initial value:
Rev. 1.00 Oct. 01, 2007 Page 266 of 1956
REJ09B0256-0100
priority.
A. Interrupts to be accepted in the device driver (interrupts to be used by the operating system:
B. Interrupts to be disabled in the device driver
accessed by the device driver in which interrupts should be disabled.
R/W:
R/W:
Bit:
Bit:
a timer interrupt etc.)
On-chip module Interrupt Priority Registers (INT2PRI0 to INT2PRI13)
31
15
−
−
R
R
0
0
30
−
14
−
R
R
0
0
29
13
−
R
−
R
0
0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
26
10
0
0
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
23
−
−
R
R
0
7
0
−
−
22
R
R
0
6
0
21
−
−
R
R
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0