r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1106

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 26 I
26.3.7
Rev. 1.00 Oct. 01, 2007 Page 1040 of 1956
REJ09B0256-0100
Bit
7
6
5
4
3
2
1
0
Master Interrupt Enable Register (ICMIER)
2
C Bus Interface (IIC)
Bit Name
—
MNRE
MALE
MSTE
MDEE
MDTE
MDRE
MATE
Initial value:
R/W:
Initial Value
0
0
0
0
0
0
0
0
BIt:
R
7
0
−
MNRE MALE
R/W
6
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
5
0
MSTE MDEE MDTE MDRE MATE
R/W
4
0
Description
Reserved
The write value should always be 0.
Master Nack Received Interrupt Enable
0: Disables the MNR interrupt.
1: Enables the MNR interrupt.
Master Arbitration Lost Interrupt Enable
0: Disables the MAL interrupt.
1: Enables the MAL interrupt.
Master Stop Transmitted Interrupt Enable
0: Disables the MST interrupt.
1: Enables the MST interrupt.
Master Data Empty Interrupt Enable
0: Disables the MDE interrupt.
1: Enables the MDE interrupt.
Master Data Transmitted Interrupt Enable
0: Disables the MDT interrupt.
1: Enables the MDT interrupt.
Master Data Received Interrupt Enable
0: Disables the MDR interrupt.
1: Enables the MDR interrupt.
Master Address Transmitted Interrupt Enable
0: Disables the MAT interrupt.
1: Enables the MAT interrupt.
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0