r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1150

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.9
SCFCR performs data count resetting and trigger data number setting for transmit and receive
FIFO registers, and also contains a loopback test enable bit.
SCFCR can always be read from and written to by the CPU.
Rev. 1.00 Oct. 01, 2007 Page 1084 of 1956
REJ09B0256-0100
Initial value:
Bit
15 to 11
10
9
8
7
6
R/W:
BIt:
FIFO Control Register (SCFCR)
Bit Name
—
RSTRG2
RSTRG1
RSTRG0
RTRG1
RTRG0
15

R
0
14

R
0
13

R
0
Initial
Value
All 0
0
0
0
0
0
12

R
0
11

R
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
RST
RG2
10
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SCIF_RTS Output Active Trigger
The SCIF_RTS signal becomes high when the number
of receive data stored in SCFRDR exceeds the trigger
number shown below.
000:63
001:1
010:8
011:16
100:32
101:48
110:54
111:60
Receive FIFO Data Number Trigger
These bits are used to set the number of receive data
bytes that sets the RDF flag in SCFSR.
The RDF flag is set when the number of receive data
bytes in SCFRDR is equal to or greater than the trigger
set number shown below.
00:1
01:16
10:32
11:48
R/W
RST
RG1
0
9
R/W
RST
RG0
8
0
RTRG1
R/W
7
0
RTRG0
R/W
6
0
TTRG1
R/W
5
0
TTRG0
R/W
4
0
R/W
MCE
3
0
TFCL
R/W
2
0
RFCL
R/W
1
0
LOOP
R/W
0
0