r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 851

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

23.2
Table 23.1 lists the pin configuration of the GETHER.
Table 23.1 Pin Configuration
Name
Transmit clock
Transmit enable
MII/GMII
transmit data
GMII transmit
data
Collision
detection
Transmit error
Receive clock
Receive data
valid
MII/GMII receive
data
GMII receive
data
Receive error
Carrier detection
Management
data clock
Management
data I/O
Input/Output Pins
Port
0
Abbreviation
ET0_TX-CLK
ET0_TX-EN
ET0_ETXD3 to
ET0_ETXD0
GET0_ETXD7 to
GET0_ETXD4
ET0_COL
ET0_TX-ER
ET0_RX-CLK
ET0_RX-DV
ET0_ERXD3 to
ET0_ERXD0
GET0_ERXD7 to
GET0_ERXD4
ET0_RX-ER
ET0_CRS
ET0_MDC
ET0_MDIO
I/O
Input
Output
Output
Output
Input
Output
Input
Input
Input
Input
Input
Input
Output
I/O
Section 23 Gigabit Ethernet Controller (GETHER)
Indicates that transmit data is ready on
Collision detection signal
Notifies PHY-LSI of error during
Identifies error state occurred during data
Carrier detection signal
Reference clock signal for information
Bidirectional signal for exchange of
Function
ET0_TX-EN, ET0_ETXD3 to
ET0_ETXD0, ET0_TX-ER timing
reference signal
ET0_ETXD3 to ET0_ETXD0
4-bit MII transmit data or lower four bits of
GMII transmit data
Upper four bits of GMII transmit data
transmission
ET0_RX-DV, ET0_ERXD3 to
ET0_ERXD0, ET0_RX-ER timing
reference signal
Indicates that valid receive data is on
ET0_ERXD3 to ET0_ERXD0
4-bit MII receive data or lower four bits of
GMII receive data (MII and GMII)
Upper four bits of GMII receive data
reception
transfer via ET0_MDIO
management information between STA
and PHY
Rev. 1.00 Oct. 01, 2007 Page 785 of 1956
REJ09B0256-0100